5 Stage Pipeline CPU
2025
- Designed a pipelined RISC-V CPU in Logisim with the classic five-stage pipeline.
- Built the datapath and control to execute a subset of the RISC-V instruction set.
- Handled pipeline hazards with data forwarding and stalling for correct execution.
Collaborators
Links / info
Overview
This was the final project for CS 61C (Great Ideas in Computer Architecture). I designed a pipelined RISC-V CPU in Logisim. The processor implements the classic five-stage pipeline, instruction fetch, decode, execute, memory, and write-back, so multiple instructions are in flight at the same time and the processor can start a new instruction before the previous one finishes.
What I built
I built the datapath and control logic to run a subset of the RISC-V instruction set, wiring together the register file, ALU, memory, and the pipeline registers between each stage. Overlapping instructions introduce hazards, so I implemented data forwarding and stalling so that dependent instructions still compute the correct result. Building a working processor from logic up made the abstract idea of pipelining concrete.